71. G. S. Lin and you can J. B. Kuo, “Fringing-Caused Thin-Channel-Effect (FINCE) Relevant Capacitance Behavior regarding Nanometer FD SOI NMOS Equipment Using Mesa-Isolation Through three dimensional Simulator” , EDSM , Taiwan ,

72. J. B. Kuo, “Development from Bootstrap Approaches to Low-Voltage CMOS Digital VLSI Circuits for SOC Programs” , IWSOC , Banff, Canada ,

P. Yang, “Entrance Misalignment Feeling Relevant Capacitance Decisions off a good 100nm DG FD SOI NMOS Unit having letter+/p+ Poly Ideal/Base Entrance” , ICSICT , Beijing, Asia

73. Grams. Y. Liu, N. C. Wang and J. B. Kuo, “Energy-Successful CMOS Higher-Stream Driver Routine towards Subservient Adiabatic/Bootstrap (CAB) Way of Lower-Energy TFT-Lcd System Programs” , ISCAS , Kobe, The japanese ,

74. Y. S. Lin, C. H. Lin, J. B. Kuo and you may K. W. Su, “CGS Capacitance Sensation from 100nm FD SOI CMOS Products with HfO2 High-k Gate Dielectric Offered Vertical and you can Fringing Displacement Outcomes” , HKEDSSC , Hong kong ,

75. J. B. KUo, C. H. Hsu and C. P. Yang, “Gate-Misalignment Relevant Capacitance Behavior of good 100nm DG SOI MOS Devices having Letter+/p+ Top/Bottom Door” , HKEDSSC , Hong-kong ,

76. G. Y. Liu, Letter. C. Wang and J. B. Kuo, “Energy-Productive CMOS Highest-Load Driver Routine into Complementary Adiabatic/Bootstrap (CAB) Technique for Reduced-Fuel TFT-Liquid crystal display System Apps” , ISCAS , Kobe, The japanese ,

77. H. P. Chen and you will J. B. Kuo, “An excellent 0.8V CMOS TSPC Adiabatic DCVS Reason Circuit towards the Bootstrap Strategy to own Lowest-Stamina VLSI” , ICECS , Israel ,

B. Kuo, “A book 0

80. J. B. Kuo and you may H. P. Chen, “A reduced-Current CMOS Weight Driver into the Adiabatic and you may Bootstrap Strategies for Low-Strength Program Applications” , MWSCAS , Hiroshima, The japanese ,

83. Meters. T. Lin, Elizabeth. C. Sunshine, and you will J. B. Kuo, “Asymmetric Door Misalignment Affect Subthreshold Functions DG SOI NMOS Products Considering Fringing Electronic Field effect” , Electron Products and you will Material Symposium ,

84. J. B. Kuo, Age. C. Sunshine, and you can Meters. T. Lin, “Investigation of Gate Misalignment Impact on the brand new Endurance Voltage off Twice-Gate (DG) Ultrathin FD SOI NMOS Devices Playing with a tight Model Offered Fringing Electronic Field effect” , IEEE Electron Devices having Microwave oven and you may Optoelectronic Software ,

86. E. Shen and J. 8V BP-DTMOS Articles Addressable Thoughts Mobile Routine Based on SOI-DTMOS Processes” , IEEE Appointment towards the Electron Equipment and you will Solid-state Circuits , Hong kong ,

87. P. C. Chen and you can J. B. Kuo, “ic Logic Circuit Using a direct Bootstrap (DB) Technique for Lowest-current CMOS VLSI” , Globally Symposium with the Circuits and you will Assistance ,

89. J. B. Kuo and you can S. C. Lin, “Compact Dysfunction Design to have PD SOI NMOS Gizmos Offered BJT/MOS Effect Ionization for Spice Circuits Simulation” , IEDMS , Taipei ,

ninety. J. B. Kuo and S. C. Lin, “Compact LDD/FD SOI CMOS Tool Design Considering Opportunity Transportation and you will Care about Temperatures to have Liven Routine Simulation” , IEDMS , Taipei ,

91. S. C. Lin and you will J. B. Kuo, “Fringing-Caused Barrier Minimizing (FIBL) Outcomes of 100nm FD SOI NMOS Equipment with high Permittivity Door Dielectrics and LDD/Sidewall Oxide Spacer” , IEEE SOI Meeting Proc , Williamsburg ,

ninety five. J. B. Kuo and S. C. Lin, “Brand new Fringing Digital Field-effect towards the Small-Station Impact Threshold Voltage out of FD SOI NMOS Products having LDD/Sidewall Oxide Spacer Construction” , Hong kong Electron Devices Fulfilling ,

93. C. L. Yang and you will J. B. Kuo, “High-Temperatures Quasi-Saturation Brand of Highest-Current https://kissbrides.com/no/jswipe-anmeldelse/ DMOS Power Gadgets” , Hong kong Electron Devices Fulfilling ,

94. Age. Shen and J. B. Kuo, “0.8V CMOS Articles-Addressable-Memories (CAM) Telephone Ciurcuit which have a fast Level-Evaluate Effectiveness Having fun with Vast majority PMOS Vibrant-Tolerance (BP-DTMOS) Technique Predicated on Important CMOS Tech to own Lowest-Voltage VLSI Systems” , All over the world Symposium towards Circuits and you will Systems (ISCAS) Proceedings , Washington ,